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SSM1105V
Scalar System Memory (SSM) for Image Processor ICs
NOT FOR NEW DESIGN
FEATURES SUMMARY s System solution for use with image processing scalar ICs - For LCD monitors, projectors, and TVs - Compatible with Pixelworks PW11x/PWx64 families (and similar image processors or micro-controllers)
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decoders, chip-selects, inverters; and to prioritize interrupts from DDC, I2C, PWM Figure 1. Packages
Single integrated package, including: - Dual bank Flash memories - DDC, I2C, and PWM channels - General purpose I/O - Programmable logic - In-System Programming via JTAG
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Dual bank Flash memories - Provide concurrent operation - 5 Mbit main Flash memory - 384 Kbit secondary Flash memory (divided into 10 small sectors) - Programmable Decode PLD for flexible address mapping of both memories
TQFP100 (U)
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Dual Display Data Channels (DDC) - Supports DDC for both analog RGB and digital DVI video input channels - DDC1/DDC2B VESA standard compliant - 256 byte SRAM buffer for each DDC channel
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In-System Programming (ISP) with JTAG - Program entire chip in 30-40 seconds with no involvement of the processor - Program with low-cost FlashLINK
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Dual independent I2C channels - Each capable of master or slave operation - Control A/D converters, video decoders, and future devices (tuner, audio, etc.)
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Content Security: Programmable Security Bit blocks access of device programmers / readers Zero-Power Technology: memory and PLD blocks automatically switch to stand-by current between input changes Package and Specifications - 100-pin TQFP, 14 x 14mm - 90 ns memory access time - VCC Operating Voltage: 2.7V to 3.6V
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Four Pulse Width Modulator (PWM) channels - 16-bit resolution for period and for duty cycle - 16-bit clock prescalers
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Seven I/O ports with 52 I/O pins for Multifunction I/O: GPIO, DDC, I2C, PWM, PLD I/O, and JTAG 3000 gate PLD with 16 macrocells, for creating glue logic, state machines, clock dividers,
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November 2002
This is information on a product still in production but not recommended for new designs.
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SSM1105V
SUMMARY DESCRIPTION SSM1105V devices bring in-system programmable (ISP) and in-application programmable (IAP) flash memory to LCD monitor, projector and television applications utilizing a scalar IC from either Pixelworks or other similar image processors or micro-controllers (MCU). Figure 3 shows a typical SSM based system with Pixelworks processor. The SSM1105V devices feature a dual -bank flash architecture, Dual Display Data Channels (DDC), I2C, PWM channels, general purpose I/O, programmable logic, and in-system programming via either JTAG or I2C.
The dual-bank Flash memory architecture supports full concurrent operation permitting IAP in the field, which means that firmware can be remotely updated with little interruption of system operation. During run-time, the secondary Flash memory array is ideal for EEPROM emulation, thus eliminating the need for a separate external EEPROM. An on-chip, decode PLD provides for flexible address mapping for both memories. Dual 256 byte SRAMs provide buffer storage for the DDC channels, thus removing the burden from the processor.
Figure 2. SSM Block Diagram
CPU ADDR AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15
INTERNAL ADDR, DATA, CONTROL BUS LINKED TO CPU SECURITY LOCK PAGE REG MAIN FLASH
10 BLOCKS, 64 KB
I/O PORT TO PLD IN BUS PD0 PD1 PD2 PD3
640 KBytes total SECONDARY FLASH 6 BLOCKS, 8 KB 48 KBytes total DDC SRAMs 256 byte 256 byte RUNTIME CONTROL REG FILES DDC I2C PWM GPIO POWER MNGMT
FS0-9 DECODE PLD CSBOOT0-5
I/O PORT PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
DDC-SRAM
CSIP PLD INPUT BUS CPU DATA PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 CSIOP
I/O PORT PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
GENERAL PLD AND ARRAY A B A B A B A B A B A B A B A B
16 OUTPUT MICROCELLS A B A B A B A B A B A B A B A B C C C C C C C C I/O PORT PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
24 INPUT MICROCELLS
CPU CNTL CNTL0 CNTL1 CNTL2 RST\ PIN FEEDBACK NODE FEEDBACK INTERNAL ADDR, DATA, CONTROL BUS LINKED TO CPU JTAG ISP CONTROLLER DUAL DDC DDC0 DDC1 QUAD PWM
PW0 PW1 PW2 PW3
DUAL I2C I2C0 I2C1
I/O PORT PPPPPPPP EEEEEEEE 01234567
I/O PORT PPPPPPPP HHHHHHHH 01234567
I/O PORT PPPP PPPP IIIIIIII 01234567
AI04976
Note: Additional address lines can be brought in to the device via Port A, B, C or D.
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SSM1105V
Table 1. Pin Assignments - TQFP100
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Assign ments PD2 PD3 GND VDD ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 GND VDD ADIO12 ADIO13 ADIO14 ADIO15 RESET CNTL2 PG0 Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin Assign ments PG1 PG2 PG3 PG4 PG5 PG6 PG7 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 VDD GND PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin Assign ments PI0 PI1 PI2 PI3 PI4 PI5 PI6 PI7 GND VDD PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND VDD PA0 PA1 PA2 PA3 PA4 Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Assign ments PA5 PA6 PA7 CNTL0 CNTL1 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VDD GND PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PD0 PD1
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SSM1105V
Figure 3. SSM1105V-Based System Applications
ANALOG RBG DDC
ADC DDC
ADDR DATA ROMOE ROMWE BHE CPU INTFC DDC / I2C Logic analog or digital Inputs 384Kb FLASH PLD - 16 MACRO CELLS 4 Channels PWM 8 GPIO 8 GPIO
PWM PWM PWM PWM CONTROL KEYBD
5 Mb FLASH I2C I2C
DVI TMDS R,G,B,CLK OPTIONAL VIDEO INPUT
I2C
Pixelworks PW11x PWx64
BACKLIGHT VOLUME TREBEL BASS
I2C MASTER/ SLAVE I2C MASTER/ SLAVE
I2C I2C
Future FEATURES
MANU FACTUR ING
JTAG In-Sytem Programming (ISP)
JTAG
DISPLAY DATA
TFT DISPLAY
AI04977
SSM1105V
Table 2. Ordering Information Scheme
Example: Device Type SSM1105 = SSM for image processor ICs Operating Voltage V = VCC = 2.7 to 3.6V Speed 90 = 90 ns Package T = TQFP100 Temperature Range 1 = 0 to 70 C (commercial) Option T = Tape & Reel Packing SSM1105 V - 90 T 1 T
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PANEL CONTROLS
OPTIONAL NTSC/PAL DECODER
YUV

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